DJEL

Founded by Yu Zongchang in 2014

Manage semiconductor yield with inspection and lithography tools

Pricing model

Demo

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★ Mixed Reviews

Time to value

Requires Expertise

You can use DJEL to improve chip manufacturing yield through a suite of hardware and software products. It includes electron beam inspection equipment (EBI) for detecting wafer defects, CD-SEM and DR-SEM for measuring critical dimensions and reviewing defects, OPC software for lithography mask optimization, PanGen Sim for photolithography process simulation, and YieldBook for integrated yield management combining data from equipment and upstream design tools.

What DJEL does

Scan wafer surfaces with electron beams to find defectsMeasure critical dimensions of semiconductor structuresClassify defects automatically using ADC algorithmsSimulate lithography process windows for new chip nodesOptimize mask patterns to improve production yieldAggregate yield data across design and manufacturing stagesReview individual defects at high resolution with energy spectrum dataMonitor fabrication process health using FDC and PWQ modulesElectron beam defect inspection (EBI) for 300mm wafers with automatic defect classificationCD-SEM critical dimension measurement supporting 150mm, 200mm, and 300mm wafer processesDR-SEM high-resolution defect review with energy spectrum analysisOPC computational lithography using inverse lithography technology and deep learningPanGen Sim strict photolithography simulation using vector optical modelsYieldBook yield management combining DMS, YMS, FDC, PWQ, and D2DB functionsAI-based etch model for advanced process node developmentOver 650 domestic and international invention patents filed