Bronco AI

Founded by David Zhi LuoZhang & Jeffrey Pan in 2023

Debug chip simulations and generate hardware testbenches for semiconductor verification teams

Pricing model

Demo

Rating

★ Mixed Reviews

Time to value

Quick Setup (< 1 hour)

You can use Bronco AI to automate chip design verification and debugging workflows. It analyzes massive simulation waveforms to trace failures to their root causes, categorizes nightly regression failures, and assigns them to engineers. The system accelerates testbench bring-up by generating stimulus, scoreboards, and SystemVerilog assertions directly from design specifications. It also reviews hardware documentation to spot ambiguities and creates targeted tests to close coverage holes before tape-out, integrating directly with existing electronic design automation workflows on premises or in your cloud environment.

What Bronco AI does

Analyze multi-gigabyte simulation waveformsGroup regression failures by error signatureWrite UVM testbench checkers and scoreboardsGenerate SystemVerilog assertions from specsIdentify ambiguities in technical specification documentsCreate targeted test stimulus for unhit coverage binsAutomated failure-to-fix root cause analysis on 100GB+ waveform filesClustering and auto-assignment of nightly regression test failuresAutomated generation of UVM stimulus, checkers, and scoreboardsDerivation of RTL code and SystemVerilog assertions from specsVerification plan auditing to detect specification ambiguitiesCoverage closure through targeted stimulus generation for unhit binsSupport for on-premise deployment and custom model integrations